UCR EE/CS120B: Introduction to Embedded Systems

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Lab 2: Storage Components

I. Introduction

For this lab, you are required to write a VHDL description at the behavioral level of a register file and a register with parallel load/shift. Once you have these two components, you need to write a testbench to show its correctness and download it to the XS40 board.

The register file has the following properties:

· The register file size is four (4) bytes, i.e. four rows of 8 bits. Each row (byte) is addressable.

· One write port with a write enable (WE) line and two write address lines (WA₁ and WA₀).

· Two read ports, each with an enable line and two address lines (RAE, RAA₁ and RAA₀ for read port A and RBE, RBA₁ and RBA₀ for read port B). To read/write from/to the register file, the enable line must be asserted and the address lines set up to the location needed.

· When the read enable lines are de-asserted, the read ports have a high impedance.

· clk: This signal will be used as a clock signal.

The register with parallel load/shift has the following properties:

· The register is a byte wide.

· The load and shift operations are selected by the two signal lines (SH₁ and SH₀) and are defined as follows: 00 = pass through; 01 = load input; 10 = shift left; 11 = shift right.

· clk: This signal will be used as a clock signal.

II. Implementation

Write the behavioral VHDL description for the two components described above and test your design by writing a VHDL testbench and observing the results.

III. Downloading

Once you have verified the results using Aldec HDL, check out an XS40 board and download your code. Verify the results.

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