UCR EE/CS120B: Digital Systems

---

Lab 4: FSM Design of a 4-bit counter Using Behavioral VHDL

I. Introduction

For this lab, you are required to write a behavioral VHDL description of a finite state machine (FSM) for a 4-bit counter and a testbench to show its correctness.

Inputs into your FSM will be the following:

• clk: This signal will be used as a clock signal
• rst: This signal will be used to reset your counter to 0 when it goes to '1' (active high).
• Input: A 4-bit number that will be used to load a value into the counter.
• Up/Down: This indicates if the counter will be counting up or counting down. If this signal is high, the counter should count down. If the signal is low, the counter should count up.
• Load: A one bit signal that indicates when you should load a value into the counter from the inputs. When this value goes high, you will load the value on Input into the counter.
• Enable: If this signal is high, then the counter should count. If this signal is low, the counter should stop.

II. Implementation

First come up with the FSM that will describe how this design should function using the synthesis method as discussed in class. Next, translate that into a VHDL description as described in lab and test your design by writing a VHDL testbench and observing the results.

III. Downloading

Once you have verified the results using Aldec HDL, check out an XS40 board and download your code. Verify the results.

---