UCR EE/CS120B: Digital Systems

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Lab 6: FSM+D Design

I. Introduction

The purpose of this lab is to implement a finite state machine plus datapath (FSM+D) in VHDL to calculate the Greatest Common Divisor (GCD) of 2 numbers.

The design of the GCD calculator should be divided into 2 parts - a controller and a datapath. The controller is an FSM which issues commands to the datapath based on the current state and the external inputs. This can be a behavioral description similar to Lab 4. The datapath contains a netlist of functional units like multiplexors, registers, subtractors and a comparator, and hence this design is structural similar to Lab 3. The controller basically steps through different states based on the comparison of the 2 numbers x and y. If x = y, we have finished computing the GCD, and we go to the final state and assert the data output line, and reset the FSM back to state 0. The Datapath does the actual GCD computation. It has the following components:

• Mux: takes 2 4-bit inputs and one select line. Based on the select line, it outputs either the 1st 4-bit number or the 2nd 4-bit number.
• Register: Takes a 4-bit input, an enable signal, and a clock signal. If the enable signal is high and the clock is pulsed, it stores the 4-bit number. The output is always available.
• Comparator: Takes 2 4-bit numbers, and assets one of 3 signals depending on whether the 1st number is less than, greater than or equal to the 2nd number.
• Subtractor: Takes 2 4-bit numbers, subtracts the smaller number from the larger and replaces the larger number with this result.
• Output Register: Holds the GCD value. When x = y the GCD has been found and is stored in x. Thus, x can be outputted.

The algorithm for calculating the GCD of x and y is as follows:

while (x != y) {

if (x < y)

y = y – x

else

x = x – y

}

output x

II. Implementation

Please refer to the figure given below for an example of how the design might be captured. However, your state machine can have a different number of states and different arcs, including loops. The datapath is not exactly what you need and needs to be modified accordingly. Write a testbench and verify your results.

Sample Structure of the Controller and Datapath

III. Downloading

Once you have verified your results using Aldec HDL, check out an XS40 board from the T.A. Download your code and verify your results.

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