Artifacts

DECLARATIONS

memory mport0 latency 12 width 64,

mport1 latency 12 width 64;

instruction cache icache of mport0

directmapped 64KB 4wpl;

data cache L2 of mport1

directmapped 128KB 4wpl;

data cache L1 of L2 4 way 8KB

4 wpl;

M

E

M

O

R

Y

Port0

Port1

I-Cache

D-Cache L2

D-Cache L1

PROCESSOR

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