Note: This HOWTO is based almost entirely off Prof. Vahid’s CS220 Synopsis Tutorial
(**Account setup applies to UCR only)
1. Copy the following files to your home directory: (make sure your browser doesn't add .txt to the end of the files)
2. Concatenate the following to your .profile:
profile_update.txt
$ cat .profile profile_update.txt > .profileNew
$ cp .profileNew .profile
“yes” if asked to overwrite
3. Concatenate the following with your .bashrc:
bashrc_update.txt
$ cat .bashrc bashrc_update.txt > .bashrcNew
$ cp .bashrcNew .bashrc
“yes” if asked to overwrite
4. From hill log onto soc.cs.ucr.edu:
$ ssh soc.cs.ucr.edu
5. Export the display using:
$ export DISPLAY=yourip:0.0 (case-sensitive)
1. Inside directory containing all the LC-2 files create a “work” directory:
$ mkdir work (Do not descend into new directory work)
2. Syntax checking: Use vhdlan to perform syntax checking and design analysis. vhdlan should be invoked using the following commands:
vhdlan RT_components.vhd
vhdlan LC2_ctrl.vhd
vhdlan ram_module(*).vhd (* is the number of the ram_module you wish to use)
vhdlan LC2_all.vhd
vhdlan LC2_all_TB.vhd
3. Run vhdldbx:
Note: If “Can’t Open Display” error appears, you have not properly exported the display, or your xhost is not accepting the query from soc.cs.ucr.edu
4. Select TESTBENCH_FOR_LC2_ALL from the design box.
5. Select: "Hierarchy Browser" from the "Misc" menu:
You should see a green arrow pointing at the top level entity you decided to simulate. Clicking next to this arrow will reveal any components which comprise the entity. Select each signal that you wish to trace and double-click on it. This will bring up the Synopsis Waveform Viewer, and the bottom half of the VHDL debugger will indicate that the signal is being traced.
6. Input a run-time then click Run:
1. Run the Synopsis Design Compiler by running:
$ dc_shell
2. Analyze the design:
analyze –f vhdl RT_components.vhd
analyze –f vhdl LC2_ctrl.vhd
analyze –f vhdl LC2_all.vhd
3. Elaborate the Design:
elaborate LC2_all
4. Enter: uniquify
5. Compile the Design:
compile (don't worry about warnings concerning the ram_module)
6. The change names command will change the internal named of the design to correspond to the VHDL naming conventions. The following two command specify some VHDL attributes that we need in order to simulate the gate-level design.
change_names -rules vhdl
vhdlout_architecture_name = "SYN"
vhdlout_use_packages = {"IEEE.std_logic_1164", "IEEE.std_logic_arith.all", "IEEE.std_logic_textio.all", "lsi_10k.COMPONENTS.all"}
7. Output Designs:
write -f vhdl -hierarchy -output "LC2_all_gate.vhd"
write -f db -hierarchy -output " LC2_all_gate.db"
8. Simulating the GATE-level design:
Create a new directory (outside of current directory):
Copy the following files into new directory:
LC2_all_gate.vhd
LC2_all_TB.vhd
Ram_module(*).vhd (* is the number of the ram_module you wish to use)Inside new directory create another work directory:
$ mkdir work
9. Syntax checking: Use vhdlan to perform syntax checking and design analysis. vhdlan should be invoked using the following commands:
$ vhdlan LC2_all_gate.vhd
$ vhdlan ram_module(*).vhd (* is the number of the ram_module you wish to use)
$ vhdlan LC2_all_TB.vhd
10. Same as before, simulate your gate level design using vhdldbx, as before.
11. If no errors then done.