Makefile Tutorial

# CS 10C - Makefile Tutorial

![:newline]

.Huge[*Prof. Ty Feng*]

![:newline]

.Large[UC Riverside - WQ 2026]

![:newline 6]

![:scale 50%](../utils/style/ucr_cs_logo.png)

---

---

int main(int argc, char **argv)
{
 if (argc < 2) {
 std::cerr << "Usage: myfact number"
 << std::endl;
 exit(1);
 }
 int n = atoi(argv[1]);
 std::cout << "fact(" << n << ") = "
 << fact(n) << std::endl;
 return 0;
}
```
]

int fact(int n);

#endif /* FACT_H_ */
```

### `fact.cc`
```cpp
#include "fact.h"

int fact(int n) {
    if (n == 0)
        return 1;
    return n * fact(n - 1);
}
```

### `README.md`
```markdown
# Overview

This program computes the
factorial of a number
```
]

---

# Manual approach

## Compilation

```bash
$ g++ -Wall -Werror -std=c++11 -c -o fact.o fact.cc
$ g++ -Wall -Werror -std=c++11 -c -o main.o main.cc
$ g++ -Wall -Werror -std=c++11 -o myfact main.o fact.o
$ ./myfact
Usage: myfact number
$ ./myfact 5
fact(5) = 120
```

## On the long run...

Now, what if:
- `fact.cc` changes? `main.cc` changes? `fact.h` changes?
- I want to change the compilation options?
- I want to recompile this code on another computer?
- I want to share this code?

**Solution is to automate the build process!**

---

# Introduction

---

## Definition

A **Makefile** is a file containing a set of rules used with the `make` build automation tool.

The two following commands are equivalent:

```bash
$ ls
Makefile ...
$ make
```

```bash
$ make -f Makefile
```

The set of Makefile rules usually represents the various steps to follow in order to build a program: it's the **building recipe**.

---

## Anatomy of a rule

```makefile
target: [list of prerequisites]
 [<tab> command]
```

- For **`target`** to be generated, the **`prerequisites`** must all exist (or be generated if necessary)
- **`target`** is generated by executing the specified **`command`**
- **`target`** is generated only if it does not exist, or if one of the prerequisites is more recent
    - Prevents from building everything each time, but only what is necessary

## Commenting

Lines prefixed with `#` are not evaluated

```makefile
# This is a comment
```

---

# Version 0.1

---

## Basic rules

```makefile
myfact: main.o fact.o
    g++ -Wall -Werror -std=c++11 -o myfact main.o fact.o

main.o: main.cc fact.h
    g++ -Wall -Werror -std=c++11 -c -o main.o main.cc

fact.o: fact.cc fact.h
    g++ -Wall -Werror -std=c++11 -c -o fact.o fact.cc
```

```bash
$ make
g++ -Wall -Werror -std=c++11 -c -o main.o main.cc
g++ -Wall -Werror -std=c++11 -c -o fact.o fact.cc
g++ -Wall -Werror -std=c++11 -o myfact main.o fact.o
```

---

## `all` rule

```makefile
all: myfact

myfact: main.o fact.o
    g++ -Wall -Werror -std=c++11 -o myfact main.o fact.o

main.o: main.cc fact.h
    g++ -Wall -Werror -std=c++11 -c -o main.o main.cc

fact.o: fact.cc fact.h
    g++ -Wall -Werror -std=c++11 -c -o fact.o fact.cc
```

```bash
$ make
g++ -Wall -Werror -std=c++11 -c -o main.o main.cc
g++ -Wall -Werror -std=c++11 -c -o fact.o fact.cc
g++ -Wall -Werror -std=c++11 -o myfact main.o fact.o
```

---

## `clean` rule

```makefile
all: myfact

...

clean:
    rm -f myfact main.o fact.o
```

```bash
$ make
g++ -Wall -Werror -std=c++11 -c -o main.o main.cc
g++ -Wall -Werror -std=c++11 -c -o fact.o fact.cc
g++ -Wall -Werror -std=c++11 -o myfact main.o fact.o
$ make clean
rm -f myfact main.o fact.o
```

---

## A first and basic Makefile

```makefile
all: myfact

myfact: main.o fact.o
    g++ -Wall -Werror -std=c++11 -o myfact main.o fact.o

main.o: main.cc fact.h
    g++ -Wall -Werror -std=c++11 -c -o main.o main.cc

fact.o: fact.cc fact.h
    g++ -Wall -Werror -std=c++11 -c -o fact.o fact.cc

clean:
    rm -f myfact main.o fact.o
```

---

# Version 0.1

---

## How to avoid redundancy...?

*A good programmer is a lazy programmer!*

<pre><code class="makefile">all: myfact

myfact: main.o fact.o
 g++ -Wall -Werror -std=c++11 -o myfact main.o fact.o

main.o: main.cc fact.h
 g++ -Wall -Werror -std=c++11 -c -o main.o main.cc

fact.o: fact.cc fact.h
 g++ -Wall -Werror -std=c++11 -c -o fact.o fact.cc

clean:
 rm -f myfact main.o fact.o
</code></pre>

---

# Version 1.0

---

## Using Variables

- Use variables to avoid redundancy
- `CXX` for the C++ compiler
- `CXXFLAGS` for compiler flags
- Reference variables with `$(VAR_NAME)`

```makefile
CXX      := g++
CXXFLAGS := -Wall -Werror -std=c++11

all: myfact

myfact: main.o fact.o
    $(CXX) $(CXXFLAGS) -o myfact main.o fact.o

main.o: main.cc fact.h
    $(CXX) $(CXXFLAGS) -c -o main.o main.cc

fact.o: fact.cc fact.h
    $(CXX) $(CXXFLAGS) -c -o fact.o fact.cc

clean:
    rm -f myfact main.o fact.o
```

```bash
$ make
g++ -Wall -Werror -std=c++11 -c -o main.o main.cc
g++ -Wall -Werror -std=c++11 -c -o fact.o fact.cc
g++ -Wall -Werror -std=c++11 -o myfact main.o fact.o
```

- Good enough for CS 10C!