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We have developed a synthesizable VHDL model of the LC-2 processor, which is a simple programmable processor defined in the popular introductory textbook: Introduction to Computing Systems: From Bits and Gates to C and Beyond , by Yale N. Patt and Sanjay J. Patel. The processor supports 16 basic instructions and each instruction is 16-bits long. The processor consists of five basic parts: memory, a processing unit, input, output, and a control unit. The processor has a memory address space of 64k (from x0000 to xFFFF) that is split into 128 pages (bits [15:9]) of 512 locations (bits [8:0]). Each address can be used to address memory or a memory mapped I/O device register. The processing unit, or the data path, contains the ALU, and register. Input and output consists a keyboard for input and a monitor for output. The control unit consists of the controller, PC, and IR. The processor's instruction cycle has 7 basic stages: fetch, decode, evaluate address, operand fetch, execute, and store result. A block diagram of the processor, from Appendix C of the textbook, illustrates the various components making up the processor.
We have synthesized our synthesizable model to gates using the Synopsys Design Compiler. We have simulated both the synthesizable model and the gate model running several programs to verify correctness of the models. Below are the source files for the synthesizable model, the program files, and the gate model, for the most recent release. Needless to say, we do not, nor does the University of California at Riverside, provide any kind of warrantee for anything you read or download from this page. Note: See the archives below for a single zip file containing all of the following files.
LC-2 Files |
File Description |
| LC2_ctrl.vhd | The LC-2 controller. |
| LC2_all.vhd | The complete LC-2 processor. Structurally combines all the components. |
| RT_components.vhd | Standard components need for the data path. (ALU, Adders, etc..) |
| LC2_all_TB.vhd | Test bench for LC-2. |
| test_module(1).vhd | Module runs a program that tests all instructions. |
| LC2_all_gate.vhd | LC2_all gate level model obtain from synthesis (excluding ram_modules) |
| ram_module(1).vhd | takes an array of 12 integers and adds them together. |
| ram_module(2).vhd | Counts the number of 1's in mem[x0100] and stores result in mem[x0101]. |
| ram_module(3).vhd | Multiplies mem[x0100] and mem[x0101] and stores result in mem[x0102]. |
| ram_module(4).vhd | Counts the occurrences of a given number in and array at mem[x0100]. |
| ram_module(5).vhd | Takes 2 numbers adds them if they are between 999 and -999 it stores the solution into memory. |
| ram_module(6).vhd | Calculates Fibonacci numbers non-recursively. |
| ram_module(7).vhd | Bubble sorts an array of size 10. |
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| LC2_syn.scr | dc_shell Script |
| LC2_ram.c, Makefile | Source code to create ram_modules from .bin files. |
| LC2_GUI_ram.exe, LC2_ram.exe | WIN32 GUI Interface to create ram_modules from .bin files.(LC2_ram required) WIN32 executable. |
Here are some of the statistics we obtained by synthesizing the LC-2 model down to gate level, using the Synopsys Design Compiler with medium mapping effort. We left the ram_modules in behavioral level code since they would normally not be synthesized into logic but rather loaded into a memory.
Component |
I/O Ports |
Combinational Area (gates) |
Sequential Area (gates) |
Critical Path (ns) |
Max Clock(MHz) |
Synth. Time (sec) |
| LC2_ctrl | 55 | 577 | 545 | 1.31 | 763 | 52 |
| LC2_alu | 50 | 242 | 0.0 | 20.30 | 49 | 16 |
| LC2_reg_bank | 59 | 766 | 1504 | 1.37 | 730 | 33 |
| LC2_all | 2 | 2781 | 4886 | n/a | n/a | 190 |
Complete set of files for releases, starting with the most recent, which are the files listed individually above.
Archive |
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| LC-2 rev 1.1.zip | 8/19/2002 | LC-2 revision 1.1 (Inital Release) |
